The present disclosure relates to electronic design automation (EDA), and more particularly to validating integrated circuit (IC) design intents requiring multi-patterning technique or technology (MPT) by incrementally validating a portion of a design intent at a time.
Improvements in semiconductor process technology can increase the pattern density of shapes printed into a process layer on the surface of a wafer below the minimum manufacture-able line-and-space-width, hereinafter also referred to as “minimum pitch”, that is achievable using just a single mask to pattern the process layer for a given generation of photolithography printing technology. As an example, double patterning technique or technology (DPT) is a type of MPT that has been used for manufacturing a design intent, hereinafter also referred to as “layout pattern,” “layout,” “design shapes,” “shapes,” “layout layer,” or “layer,” having more than a single pitch within the spacing of a single minimum pitch that is printable by using just a single photolithographic mask. DPT uses two different masks to produce higher pattern surface density in a process layer of the design intent than is achievable by using just one mask to print that layer. However, multi-patterning technology requires special design rules, EDA, and wafer processing procedures that are more complicated than standard photolithography printing technology. In particular, iteratively checking, hereinafter also referred to as iteratively “validating,” a MPT design intent uses considerable computing resources and time.
Accordingly, there is a need to save computing resources and time for validation of design intents using MPT.